1. The Field of the Invention
The invention relates generally to optoelectronic/optical transponders and particularly to optoelectronic/optical transponder modules including a controller chip that interprets signals differently than a host device.
2. The Relevant Technology
Digital data can be efficiently propagated through a fiber-optic cable using light signals from light emitting diodes or lasers. To send data on a fiber-optic cable, the data is typically converted from electronic data generated by computers to optical data that can be propagated onto the fiber-optic cable. When data is received from a fiber-optic cable, the data must be converted from optical data to electronic data so that it can be received by a computer.
A transmitter optical subassembly (TOSA) is often used to convert electronic data to optical data for transmission on a fiber-optic cable. A TOSA uses the electronic data to drive a laser diode or light emitting diode to generate the optical data. When optical data is converted to electronic data, a receiver optical subassembly (ROSA) is used. The ROSA has a photo diode that, in conjunction with other circuitry, converts the optical data to electronic data. Because most computers both transmit and receive data, most computers need both a TOSA and a ROSA to communicate through fiber-optic cables. A TOSA and ROSA can be combined into an assembly generally referred to as a transponder.
Optical transponders are used for receiving and transmitting data between electronic hosts such as computers using an optical network. Generally, optical transponders are located at the interface of an optical network and an electronic host to receive optical data from the network, convert the optical data to electronic data, and to pass on the electronic data to the host. Likewise, optical transponders also receive electronic data from the host, convert the electronic data to optical data, and transmit the optical data through an optical network to another host. Optical transponders commonly come in the form of a transponder module that can be mounted on a motherboard of a host.
A controller chip located in the transponder module manages the data conversion between optical data and electronic data. One function of the controller chip is clock extraction, or extraction of a reference clock signal that is embedded in the data. Clock extraction allows the controller chip to provide the reference clock signal to the host device so that the data can be accurately read at appropriate times by the host device. Another function of the controller chip is sampling the data. Once the clock is extracted and the data is sampled, the clock reference signal is used as a reference for converting the sampled data into synchronized data that can be easily read by the host device. This synchronized data is synchronized to the reference clock signal that is at a predetermined target frequency (e.g., 10 Gigabits per second).
Although the target frequency of the incoming data is generally known, the controller chip must determine the exact moments at which data can be sampled to detect each data bit. To make this determination, the controller chip may use a phase-locked-loop (PLL) to “hunt” a range of frequencies in the incoming data stream to locate a signal. When the PLL is in hunting mode, the PLL searches within a predetermined frequency range that includes the target frequency. When the reference clock signal is found, the PLL locks onto the reference clock signal so that from that point on, data can be sampled regularly at the target frequency to read every data bit.
Manufacturers of the controller chip may configure the controller chip to produce a logical “0” when the PLL hunting frequency is different from the target frequency of the incoming data, and to produce a logical “1” when the PLL hunting frequency overlaps with the target frequency. This type of logic is commonly referred to as “asserted high” and “deasserted low.” Thus, if the predetermined frequency is 10 Gigabits per second and the PLL is hunting in the frequency range of 9.5 Gigabits per second to 10.5 Gigabits per second, a logical “1” is produced for a short period of time at a regular interval, or each time the PLL oscillates through the target frequency of 10 Gigabits per second.
Alternatively, manufacturers of the controller chip may configure the controller chip to produce a logical “1” when the hunting frequency is different than the target frequency and a logical “0” when the hunting frequency overlaps with the target frequency. This type of logic may commonly be referred to as “asserted low” and “deasserted high.” The asserted logical value is the value indicating that the hunting frequency is at the target frequency whereas the deasserted logical value is the value indicating that the hunting frequency is not at the target frequency. In either case, the controller chip produces a number of false short lock signals, whether they be asserted high or low, in hunting mode that may be passed to the host device. The host device may misinterpret these signals. As such, the host device may try to read data from the controller chip when no valid data exits.